Electronic Design

Synopsys And UMC Beef Up 90-nm Reference Flow

Synopsys and UMC combine forces to enhance the capabilities of their jointly developed 90-nm reference design flow. It now includes an automated multiple voltage (multi-Vdd) capability that can ...
EDN

Synopsys DFT tool gets core add on

SAN MATEO, Calif.—Synopsys Inc. Monday (March 3) announced it has added new features to SoCBIST, an add-on to DFT Compiler for the creation and integration of IP cores that are optimized for test ...
Design-Reuse

Synopsys and Virage Logic Collaborate on Test Reference Design Flow to Deliver Embedded Memory Test

Comprehensive Test Flow Links Galaxy Platform With STAR Memory System MOUNTAIN VIEW, Calif. and FREMONT, Calif. -- Oct. 23, 2006-- Synopsys, Inc., a world leader in semiconductor design software, and ...
EDN

ITC 2008: Synopsys touts DFT MAX compression adoption at 90 nm

Synopsys announced at the International Test Conference that its DFT MAX compression product has been successfully deployed at more than one hundred semiconductors companies from all industry segments ...
Design-Reuse

Synopsys IC Compiler Enables Fully Automated 65-Nanometer Implementation Flow For ARM Cortex-A8 Processor

Flow delivers a 5-10X boost in productivity for mobile and consumer applications MOUNTAIN VIEW, CA AND CAMBRIDGE, UK—Mar. 28, 2007—Synopsys, Inc. (Nasdaq: SNPS), a world leader in semiconductor ...