SAN JOSE, Calif. — MIPS Technologies Inc. is upgrading two of its cores and introducing a new instruction set architecture. The products aim to expand the company's relatively small presence in 32-bit ...

MIPS Technologies is now offering the Pro Series family of synthesizable cores supporting accelerated, application-specific instructions within the MIPS instruction set. These cores add MIPS CorExtend ...

Agreement with MIPS Technologies Enables Model Availability to Speed Development of Robust, Optimized MIPS-Based Products SAN JOSE, Calif. and MOUNTAIN VIEW, Calif. – August 18, 2008-- CoWare®, Inc.

The MIPS SIMD architecture (MSA) module allows efficient parallel processing of vector operations. This functionality is of growing importance across a range of applications. For consumer electronics ...

The academy in charge of advancing China’s homegrown microprocessors has licensed the MIPS chip architecture, burying an old controversy over its use of parts of the MIPS instruction set. China’s ...

The Multi IDE now supports the MIPS 32-bit 24K cores—including the 24Kc, 24Kc Pro, 24Kf, and 24Kf Pro—that operate up to 500 MHz. It also supports the company's C, C++, EC++, and Ada95 compilers. Its ...

Wave Computing has made good on its promise of making the MIPs instruction set architecture (MIPS) available free of charge, announcing the first release in what it is calling the MIPS Open initiative ...